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| DATA SHEET MOS Integrated Circuit PD75P036 4-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The PD75P036 is a 4-bit signgle-chip microcontroller that replaced the PD75028's on-chip ROM with one-time PROM or EPROM. Because this device can operate at the same supply voltage as its mask version, it is suited for preproduction in development stage or small-scale production. The one-time PROM version is programmable only once and is useful for small-scale production of many different products and time-to-market of a new product. The EPROM version is programmable, erasable, and reprogrammable, and is suited for the evaluation of application systems. Detailed functions are described in the followig user's manual. Be sure to read it for designing. 5 PD75028 User's Manual: IEU-1280 FEATURES * * PD75028 compatible * At full production, the PD75P036 can be replaced with the PD75028 which incorporates mask ROM Memory capacity * Program memory (PROM): 16256 x 8 bits * Data memory (RAM): 1024 x 4 bits * * * * Internal pull-up resistors can be specified by software: Ports 0-3, 6-8 Internal pull-down resistors can be specified by software: Port 9 Open-drain input/output: Ports 4, 5, 10 Can operate at low voltage: VDD = 2.7 to 6.0 V ORDERING INFORMATION Part Number Package 64-pin plastic shrink DIP (750 mils) 64-pin plastic QFP (14 x 14 mm) 64-pin ceramic WQFN Internal ROM One-time PROM One-time PROM EPROM Quality Grade Standard Standard Not applicable 5 PD75P036CW PD75P036GC-AB8 PD75P036KG Caution Internal pull-up/pull-down resistors cannot be specified by mask option as for this device. Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on e devices and its recommended applications. The reliability of the EPROM version, PD75P036KG, is not guaranteed when used in mass-produced application sets. Please use this device only experimentally or for evaluation during trial manufacture. The function common to the one-time PROM and EPROM versions is referred to as PROM throughout this document. The information in this document is subject to change without notice. Document No. U10051EJ3V0DS00 (3rd edition) (Previous No. IC-2967 Date Published September 1995 P Printed in Japan The mark 5 shows revised points. (c) NEC Corporation 1991 PD75P036 PIN CONFIGURATIONS (Top View) * 64-pin plastic shrink DIP (750 mils) SB1/SI/P03 SB0/SO/P02 SCK/P01 INT4/P00 BUZ/P23 PCL/P22 PPO/P21 PTO0/P20 MAT/P103 MAZ/P102 MAI/P101 MAR/P100 RESET X1 X2 VPP XT1 XT2 VDD AVDD AVREF+ AVREFAN7 AN6 AN5 AN4 AN3/P113 AN2/P112 AN1/P111 AN0/P110 AVSS TIO/P13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VSS P30/MD0 P31/MD1 P32/MD2 P33/MD3 P40 P41 P42 P43 P50 P51 P52 P53 P60/KR0 P61/KR1 P62/KR2 P63/KR3 P70/KR4 P71/KR5 P72/KR6 P73/KR7 P80 P81 P82 P83 P90 P91 P92 P93 P10/INT0 P11/INT1 P12/INT2 * 64-pin plastic QFP (14 x 14 mm) * 64-pin ceramic WQFN P50 P51 P52 P53 P60/KR0 P61/KR1 P62/KR2 P63/KR3 P70/KR4 P71/KR5 P72/KR6 P73/KR7 P80 P81 P82 P83 P43 P42 P41 P40 MD3/P33 MD2/P32 MD1/P31 MD0/P30 VSS SB1/SI/P03 SB0/SO/P02 SCK/P01 INT4/P00 BUZ/P23 PCL/P22 PPO/P21 1 48 2 47 3 46 45 4 44 5 43 6 42 7 8 41 40 9 39 10 38 11 12 37 36 13 35 14 34 15 161718 19 20 21 22 23 24 25 26 2728 29 30 31 3233 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 2 PTO0/P20 MAT/P103 MAZ/P102 MAI/P101 MAR/P100 RESET X1 X2 VPP XT1 XT2 VDD AVDD AVREF+ AVREFAN7 PD75P036CW PD75P036GC-AB8 PD75P036KG P90 P91 P92 P93 P10/INT0 P11/INT1 P12/INT2 TI0/P13 AVSS AN0/P110 AN1/P111 AN2/P112 AN3/P113 AN4 AN5 AN6 PD75P036 PIN IDENTIFICATION P00-P03 P10-P13 P20-P23 P30-P33 P40-P43 P50-P53 P60-P63 P70-P73 P80-P83 P90-P93 : Port 0 : Port 1 : Port 2 : Port 3 : Port 4 : Port 5 : Port 6 : Port 7 : Port 8 : Port 9 PPO AN0-AN7 AVREF+ ABREF- AVDD AVSS VDD VSS MD0-MD3 VPP MAI MAZ MAT INT0, INT1, INT4 : External Vectored Interrupt INT2 X1, X2 XT1, XT2 MAR : External Test Input : Main System Clock Oscillation : Subsystem Clock Oscillation : Reference Integration Control : Integration Control : Autozero Control : External Comparate Timing Input : Programmable Pulse Output *** MFT timer mode : Analog Input : Analog Reference (+) : Analog Reference (-) : Analog VDD : Analog VSS : Positive Power Supply : Ground : Mode Selection : Programming/Verifying Power Supply MFT A/D mode 5 P100-P103 : Port 10 P110-P113 : Port 11 KR0-KR7 SCK SI SO SB0, SB1 RESET TI0 PTO0 BUZ PCL Remark : Key Return : Serial Clock : Serial Input : Serial Output : Serial Bus : Reset Input : Timer Input : Programmable Timer Output : Buzzer Clock : Programmable Clock MFT: Multifunction Timer 3 4 BASIC INTERVAL TIMER INTBT TIMER /COUNTER #0 INTT0 SI/SB1/P03 SO/SB0/P02 SCK/P01 SERIAL INTERFACE INTCSI INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0-KR3/P60-P63 KR4-KR7/P70-P73 BUZ/P23 PROGRAM COUNTER ALU BANK PORT 2 P20-P23 BIT SEQ. BUFFER PORT 0 SP CY PORT 1 P10-P13 P00-P03 TI0/P13 PTO0/P20 PORT 3 GENERAL REG. PROM PROGRAM MEMORY 16256 x 4 BITS DECODE AND CONTROL P30/MD0-P33/MD3 INTERRUPT CONTROL PORT 4 P40-P43 PORT 5 RAM DATA MEMORY 1024 x 4 BITS P50-P53 WATCH TIMER INTW AVDD AVREF+ AVREF- AVSS AN0-AN3/P110-P113 AN4-AN7 MAR/P100 MAI/P101 MAZ/P102 MAT/P103 PPO/P21 PORT 6 P60-P63 PORT 7 P70-P73 A/D CONVERTER fx/2N CLOCK CLOCK OUTPUT DIVIDER CONTROL CLOCK GENERATOR SUB MAIN CPU CLOCK PORT 10 P100-P103 PORT 8 P80-P83 PORT 9 P90-P93 BLOCK DIAGRAM MULTIFUNCTION TIMER STAND BY CONTROL PORT 11 PCL/P22 XT1 XT2 X1 X2 P110-P113 PD75P036 INTMFT VPP VDD VSS RESET PD75P036 CONTENTS 1. PIN FUNCTIONS ... 6 1.1 Port Pins ... 6 1.2 Non-Port Pins ... 8 1.3 Pin Input/Output Circuits ... 10 1.4 Recommended Connection of Unused Pins ... 13 MEMORY ... 14 2.1 Differences between PD75P036 and PD75028/75036 ... 14 2.2 Program Memory (ROM) ... 15 2.3 Data Memory (RAM) ... 17 WRITING AND VERIFYING PROM (PROGRAM MEMORY) ... 19 3.1 Operation Modes For Writing/Verifying Program Memory ... 19 3.2 Program Memory Write Procedure ... 20 3.3 Program Memory Read Procedure ... 21 3.4 Erasure (PD75P036KG only) ... 22 ELECTRICAL SPECIFICATIONS ... 23 CHARACTERISTIC CURVES ... 38 PACKAGE DRAWINGS ... 44 RECOMMENDED SOLDERING CONDITIONS ... 47 DEVELOPMENT TOOLS ... 48 RELATED DOCUMENTS ... 49 5 2. 3. 5 4. 5. 6. 7. 5 APPENDIX A. APPENDIX B. 5 5 PD75P036 1. PIN FUNCTIONS 1.1 Port Pins (1/2) Pin Name Input/Output Alternate Function INT4 SCK SO/SB0 SI/SBI INT0 INT1 INT2 TI0 PTO0 PPO PCL BUZ MD0 MD1 MD2 MD3 Function 8-Bit I/O When Reset Input/Output Circuit Type Note 1 P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 Note 2 P31 Note 2 P32 Note 2 P33 Note 2 Input Input/Output Input/Output Input/Output Input Input/Output 4-bit input port (PORT0). Internal pull-up resistors can be specified in 3-bit units for the P01 to P03 pins by software. With noise elimination function 4-bit input port (PORT1). Internal pull-up resistors can be specified in 4-bit units by software. 4-bit input/output port (PORT2). Internal pull-up resistors can be specified in 4-bit units by software. Programmable 4-bit input/output port (PORT3). This port can be specified for input/output in bit units. Internal pull-up resistors can be specified in 4-bit units by software. N-ch open-drain 4-bit input/output port (PORT4). Withstands up to 10 V. Data input/output pin for writing and verifying of program memory (PROM) (lower 4 bits). N-ch open-drain 4-bit input/output port (PORT5). Withstands up to 10 V. Data input/output pin for writing and verifying of program memory (PROM) (upper 4 bits). No Input No Input B F F M B -A -B -C -C No Input E-B Input/Output No Input E-B Note 2 Yes Input M-A P40-P43 Input/Output Note 2 Input/Output Input M-A P50-P53 Notes 1. Circles indicate Schmitt-triggerred inputs. 2. Can directly drive LEDs. 6 PD75P036 1.1 Port Pins (2/2) Pin Name Input/Output Alternate Function KR0 KR1 KR2 KR3 KR4 KR5 KR6 KR7 -- Function 8-Bit I/O When Reset Input/Output Circuit Type Note 1 P60 P61 P62 P63 P70 P71 P72 P73 P80-P83 Input/Output Input/Output Programmable 4-bit input/output port (PORT6). Internal pull-up resistors can be specified in 4-bit units by software. 4-bit input/output port (PORT7). Internal pull-up resistors can be specified in 4-bit units by software. 4-bit input/output port (PORT8). Internal pull-up resistors can be specified in 4-bit units by software. 4-bit input/output port (PORT9). Internal pull-up resistors can be specified in 4-bit units by software. N-ch open-drain 4-bit input/output port (PORT10). Withstands up to 10 V in open-drain mode. 4-bit input/output port (PORT11). Yes Input F -A Input F -A Input/Output No Input E-B P90-P93 Input/Output -- Input E-D P100 P101 P102 P103 P110 P111 P112 P113 Input/Output Input MAR MAI MAZ MAT AN0 AN1 AN2 AN3 No Input M -A Input Y Note Circles indicate schmitt-triggerred inputs. 7 PD75P036 1.2 Non-Port Pins (1/2) Pin Name Input/Output Alternate Function P13 P20 P22 P23 P01 P02 P03 P00 P10 P11 P12 P60-P63 P70-P73 P100 P101 P102 P103 P21 Function 8-Bit I/O When Reset Input/Output Circuit Type Note 1 TI0 PTO0 PCL BUZ SCK SO/SB0 SI/SB1 INT4 INT0 INT1 INT2 KR0-KR3 KR4-KR7 MAR MAI MAZ MAT PPO Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output External event pulse input pin to timer/event counter Timer/event counter output pin Clock output pin Fixed frequency output pin (for buzzer or for trimming the system clock) Serial clock input/output pin Serial data output pin Serial bus input/output pin Serial data output pin Serial bus input/output pin Edge detection vectored interrupt input pin (Either rising or falling edge detection is effective) Edge detection vectored interrupt input pin (Detection edge can be selected) Edge detection testable input pin (rising edge detection) Testable input/output pin (parallel falling edge detection) Testable input/output pin (parallel falling edge detection) In integral A/D Reverse integration signal output pin converter mode Integration signal output pin of MFT Auto zero signal output pin Comparator input pin In timer mode Timer pulse output pin of MFT Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input B -C E-B E-B E-B F-A F-B M-C B B -C B F F M M M M E -C -A -A -A -A -A -A -B Note Circles indicate Schmitt-triggerred inputs. Remark MFT: Multifunction timer 8 PD75P036 1.2 Non-Port Pins (2/2) Pin Name Input/Output Alternate Function P110-P113 -- -- -- -- -- -- Function When Reset Input/Output Circuit Type Note 1 AN0-AN3 AN4-AN7 AVREF+ AVREF- AVDD AVSS X1, X2 Input Input Input -- -- Input Pins only for A/D converter 8-bit analog input pin. -- -- -- -- -- -- XT1, XT2 Input -- RESET Input MD0/MD3 Input/Output VPP Note 2 -- -- P30-P33 -- VDD VSS -- -- -- -- Reference voltage input pin (AVDD side). Reference voltage input pin (AVSS side). Positive power supply pin. GND potential pin. Crystal or ceramic resonator connection for main system clock generation. To use external clock, input the external clock to X1 and its reverse phase to X2. Crystal or ceramic resonator connection for subsystem clock generation. To use external clock, input the external clock to XT1 and its reverse phase to XT2. XT1 can be used as a 1-bit input (test) pin. System reset input pin. Mode selection pins in program memory (PROM) write/verify mode. Program voltage application pin in program memory (PROM) write/verify mode. At normal operation, connect the pin to VDD directly. In the PROM write/verify mode, apply +12.5 V. Positive power supply pin. GND potential pin. Y Y -A Z -A Z -A -- -- -- -- -- -- Input -- B E-B -- -- -- -- -- Notes 1. Circles indicate schmitt trigger inputs. 2. If the VPP pin is not connected directly to the VDD pin at normal operation, the PD75P036 does not operate normally. 9 PD75P036 1.3 Pin Input/Output Circuits The following shows a simplified input/output circuit diagram for each pin of the PD75P036. TYPE A (for TYPE E - B) VDD TYPE D (for TYPE E - B, F - A) VDD data P-ch OUT output disable P-ch IN N-ch N-ch CMOS-level input buffer Push-pull output that can be set in an output high-impedance state (both P-ch and N-ch are off) TYPE B TYPE E - B VDD P.U.R. IN data output disable P.U.R. enable Type D P-ch IN/OUT Type A Schmitt-triggerred input with hysteresis characteristics P.U.R. : Pull-Up Resistor TYPE B - C VDD P.U.R. P-ch P.U.R. enable TYPE E - D data output disable Type D IN/OUT Type A P.D.R. enable IN N-ch P.D.R. P.U.R. : Pull-Up Resistor P.D.R. : Pull-Down Resistor 10 PD75P036 TYPE F - A TYPE M - C VDD P.U.R. P.U.R. enable data Type D output disable Type B VDD P.U.R. P.U.R. enable P-ch IN/OUT IN/OUT data output disable N-ch P-ch P.U.R. : Pull-Up Resistor P.U.R. : PullUp Resistor TYPE F - B VDD P.U.R. TYPE Y AVDD output disable (P) data output disable P.U.R. enable P-ch VDD P-ch IN/OUT AVSS N-ch output disable (N) P.U.R. : Pull-Up Resistor input enable IN AVDD P-ch N-ch Sampling C + - AVSS Reference voltage (from serial resistor string voltage tap) TYPE M - A TYPE Y - A IN instruction IN/OUT Input buffer data output disable N-ch (+10-V voltage) IN AVDD P-ch N-ch Sampling C AVDD + - AVSS AVSS Middle-voltage input buffer (withstands up to + 10 V) P.U.R. : Pull-Up Resistor Reference voltage (from serial resistor string voltage tap) 11 PD75P036 TYPE Z - A AVREF+ Reference voltage AVREF- 12 PD75P036 1.4 Recommended Connection of Unused Pins Pin Name P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0-P12/INT2 P13/TI0 P20/PTO0 P21/PPO P22/PCL P23/BUZ P30/MD0-P33/MD3 P40-P43 P50-P53 P60/KR0-P63/KR3 P70/KR4-P73/KR7 P80-P83 P90-P93 P100/MAR P101/MAI P102/MAZ P103/MAT P110/AN0-P113/AN3 AN4-AN7 AVREF+ AVREF- AVSS AVDD XT1 XT2 VPP Recomended Connecting Method Connect to VSS. Connect to VSS or VDD. 5 Connect to VSS. Input state: Independently connect to VSS or VDD via a resistor. Output state: Leave Open. Connect to VSS or VDD. Connect to VSS. Connect to VDD. Connect to VSS or VDD. Leave Open. Connect directly to VDD. 13 PD75P036 2. MEMORY 2.1 Differences between PD75P036 and PD75028/75036 The PD75P036 is a microcontroller provided by replacing the PD75028's on-chip mask ROM with one-time PROM or EPROM. Capacity of program memory and data memory are different, but CPU function and internal hardware are identical. Table 2-1 shows the differences between the PD75P036 and PD75028/75036. Users should fully consider these differences especially when debugging or producing an application system on an experimental basis by using the PROM version and then mass-producing the system using the mask ROM version. For details about the CPU function and the internal hardware, refer to PD75028 User's Manual (IEM-1280). 5 Item Program memory Table 2-1. Differences between PD75P036 and PD75028/75036 PD75P036 One-time PROM/EPROM 0000H-3F7FH (16256 x 8 bits) 000H-3FFH (1024 x 4 bits) Can be specified by software. Not provided Can be specified by software. Provided on-chip VDD = 2.7 to 6.0 V PD75028 Mask ROM 0000H-1F7FH (8064 x 8 bits) 000H-1FFH (512 x 4 bits) PD75036 0000H-3F7FH (16256 x 8 bits) 000H-3FFH (1024 x 4 bits) Data memory Pull-up resistor Ports 0-3, 6-8 Ports 4, 5, 10 Pull-down resistor Port 9 XT1 feedback resistor Supply voltage Pin connection Can be connected by mask option Can be disconnected by mask option Pin 16 (SDIP) VPP Internally connected Pin 25 (QFP) Pins 60-63 P33/MD3-P30/MD0 P33-P30 (SDIP) Pins 5-8 (QFP) Electrical specifications Supply current and operating temperature ranges differ between PD75P036 and PD75028/75036. For details, refer to the electrical specifications described in Data Sheet of each model. Others Noise immunity and noise radiation differ because circuit complexity and mask layout are different. Caution The noise immunity and noise radiation differ between the PROM and mask ROM versions. To replace the PROM version with the mask ROM version in the course of experimental production to mass production, evaluate your system by using the CS version (not ES) of the mask ROM version. 14 PD75P036 2.2 Program Memory (ROM) *** 16256 words x 8 bits The program memory is a 16256-word x 8-bit PROM and stores programs, table data, etc. The program memory is accessed by referencing the program counter contents. Table data can be referenced by executing a table look-up instruction (MOVT). Figure 2-1 shows the address range in which a branch can be taken by branch instructions and subroutine call instructions. A relative branch instruction (BR $addr) enables a branch to addresses [PC value -15 to -1, +2 to +16] regardless of block boundaries. Program memory addresses are 0000H-3F7FH and the following addresses are assigned to special purposes: (All areas except 0000H or 0001H can be used as normal program memory.) * Addresses 0000H-0001H Vector table into which the program start address and MBE setting value when the RESET signal is generated are written. Processing at reset is started at any desired address. * Addresses 0002H-000DH Vector table into which the program start address and MBE setting value when each vectored interrupt is generated are written. Interrupt servicing can be started at any desired address. * Addresses 0020H-007FH Table area referenced by the GETI instructionNote. Note The GETI instruction is provided to execute any 2-byte or 3-byte instruction or two 1-byte instructions as a 1byte instruction; it is used to reduce the number of program steps. 15 PD75P036 Figure 2-1. Program Memory Map Address 7 6 0 Internal reset start address (high-order six bits) Internal reset start address (low-order eight bits) 0 0 0 2 H MBE 0 INTBT/INT4 start address (high-order six bits) INTBT/INT4 start address (low-order eight bits) 0 0 0 4 H MBE 0 INT0 start address (high-order six bits) INT0 start address (low-order eight bits) 0 0 0 6 H MBE 0 INT1 start address (high-order six bits) INT1 start address (low-order eight bits) 0 0 0 8 H MBE 0 INTCSI start address (high-order six bits) INTCSI start address (low-order eight bits) 0 0 0 A H MBE 0 INT0 start address (high-order six bits) INT0 start address (low-order eight bits) 0 0 0 C H MBE 0 INTMFT start address (high-order six bits) INTMFT start address (low-order eight bits) BRCB ! caddr instruction branch address BR $ addr instruction relative branch Address (-15 to -1 and +2 to +16) CALLF ! faddr instruction entry address CALL ! addr instruction subroutine entry addres 0 0 0 0 0 H MBE BR ! addr Instruction branch address 0020H GETI instruction reference table 007FH 0080H 07FFH 0800H 0FFFH 1000H BRCB ! caddr instruction branch addresses 1FFFH 2000H BRCB ! caddr instruction branch addresses 2FFFH 3000H BRCB ! caddr instruction branch addresses 3F7FH Branch destination address and subroutine entry address to be set by GETI instruction 16 PD75P036 2.3 Data Memory (RAM) The data memory consists of a data area and a peripheral hardware area as shown in Figure 2-2. The data memory consists of banks, each consisting of 256 words x 4 bits, and the following memory banks can be used: * Memory banks 0-3 (data area) * Memory bank 15 (peripheral hardware area) Figure 2-2. Data Memory Map Data Memory General purpose register area Stack area 000H (8 x 4) 007H 008H 256 x 4 0FFH 100H 256 x 4 Data area Static RAM (1024 x 4) 1FFH 200H 256 x 4 2FFH 300H 256 x 4 3FFH Not implemented F80H 128 x 4 FFFH Memory Bank 0 1 2 3 Peripheral hardware area 15 17 PD75P036 (1) Data area The data area consists of static RAM and is used to store process data and as stack memory when a (subroutine) or an interrupt is executed. Even when CPU operation is stopped in the standby mode, the memory contents can be retained for hours with battery backup, etc. The data area is manipulated by executing memory manipulation instructions. The static RAM is mapped each 256 x 4 bits in memory banks 0-3. Bank 0 is mapped as a data area; it can also be used as a general purpose register area (000H-007H) and a stack area (000H-0FFH). One address of the static RAM consists of four bits; however it can be manipulated in 8-bit units by executing 8-bit memory manipulation instructions and bit-wise by executing bit manipulation instructions. To execute an 8-bit memory manipulation instruction, specify an even address. (a) General purpose register area Can be handled by executing general purpose register and memory manipulation instructions. A maximum of eight 4-bit registers can be used. The portions of the eight general purpose registers not used by a program can be used as a data area or stack area. (b) Stack area Is set by an instruction and can be used as a save area when a subroutine is executed or interrupt servicing is performed. (2) Peripheral hardware area The peripheral hardware area is mapped in addresses F80H-FFFH of memory bank 15. Like the static memory, the peripheral hardware area is handled by executing memory manipulation instructions. However, the bit units in which the peripheral hardware can be manipulated vary depending on the address. Addresses in which the peripheral hardware is not mapped do not contain data memory and cannot be accessed. 18 PD75P036 3. WRITING AND VERIFYING PROM (PROGRAM MEMORY) The program memory incorporated in the PD75P036 is a 16256 x 8-bit electrically writable PROM. The pins as listed in the table given below are used for write and verification of the PROM. No address is input; instead, an address is updated by inputting a clock from the X1 pin. Pin Name VPP X1, X2 Function Applies voltage when program memory is written/verified (normally, at VDD potential) These pins input clock that updates address when program memory is written/verified. To X2 pin, input X1's signal reverse phase. MD0-MD3 (P30-P33) P40-P43 (Lower 4) P50-P53 (Upper 4) VDD These pins select operation mode when program memory is written/verified. These pins input/output 8-bit data when program memory is written/verified. Power supply voltage application pin. Apply 2.7 to 6.0 V to this pin during normal operation and 6 V when program memory is written/verified. Cautions 1. Always cover the erasure window of the PD75P036KG with an opaque film except when the contents of the EPROM are erased. 2. The one-time PROM version PD75P036CW/GC is not equipped with a window, and therefore, the contents of the program memory of this model cannot be erased by exposing it to ultraviolet rays. 3.1 Operation Modes For Writing/Verifying Program Memory When +6V is applied to the VDD pin of the PD75P036 with +12.5V applied to the VPP pin, the PD75P036 is set in the program memory write/verify mode. In this mode, the following operation modes can be set by using the MD0MD3 pins. At this time, all remaining pins are set to the VSS potential with pull-down resistors. 5 Operating Mode Specification VPP +12.5 V VDD +6 V MD0 H L L H MD1 L H L X MD2 H H H H MD3 L H H H Operating Mode Program memory address 0 clear mode Write mode Verify mode Program inhibit mode x: L or H 19 PD75P036 3.2 Program Memory Write Procedure The program memory write procedure is as follows. High-speed program memory write is possible. (1) Connect the unused pins to VSS via pull-down resistors. The X1 pin must be low. (2) Supply 5 V to the VDD and VPP pins. (3) Wait for 10 s. (4) Set program memory address 0 clear mode. (5) Supply 6 V to the VDD pin and 12.5 V to the VPP pin. (6) Set program inhibit mode. (7) Write data in 1 ms write mode. (8) Set program inhibit mode. (9) Set verify mode. If data has been written connectly, proceed to step (10). If data has not yet been written, repeat steps (7) to (9). (10) Write additional data for (the number of times data was written (X) in steps (7) to (9)) times 1 ms. (11) Set program inhibit mode. (12) Supply a pulse to the X1 pin four times to update the program memory address by 1. (13) Repeat steps (7) to (12) to the last address. (14) Set program memory address 0 clear mode. (15) Change the voltages of VDD and VPP pins to 5 V. (16) Turn off the power supply. Steps (2) to (12) are illustrated below. X-time repetition Additional data write Address increment Write Verify VPP VPP VDD VDD+1 VDD VDD X1 P40-P43 P50-P53 Data input Data output Data input MD0 (P30) MD1 (P31) MD2 (P32) MD3 (P33) 20 PD75P036 3.3 Program Memory Read Procedure The PD 75P036 program memory contents can be read in the following procedure. Read operation should be performed in the verify mode. (1) Connect the unused pins to VSS via pull-down resistors. The X1 pin must be low. (2) Supply 5 V to the VDD and VPP pins. (3) Wait for 10 s. (4) Set program memory address 0 clear mode. (5) Supply 6 V to the VDD pin and 12.5 V to the VPP pin. (6) Set program inhibit mode. (7) Set verify mode. Data of each address is sequentially output each time a clock pulse is input to the X1 pin four times. (8) Set program inhibit mode. (9) Set program memory address 0 clear mode. (10) Change the voltages of VDD and VPP pins to 5 V. (11) Turn off the power supply. Steps (2) to (9) are illustrated below. VPP VPP VDD VDD+1 VDD VDD X1 P40-P43 P50-P53 Data output Data output MD0 (P30) MD1 (P31) MD2 (P32) "L" MD3 (P33) 21 PD75P036 5 3.4 Erasure (PD75P036KG only) The contents of the data programmed to the PD75P036 can be erased by exposing the window to ultraviolet rays. The wavelength of the ultraviolet rays used to erase the contents is about 250 nm, and the quantity of the ultraviolet rays necessary for complete erasure is 15 W*s/cm2 (= ultraviolet ray intensity x erasure time). When a commercially available ultraviolet ray lamp (wavelength: 254 nm, intensity: 12 mW/cm2) is used, about 15 to 20 minutes is required. Cautions 1. The contents of the program memory may be erased if the PD75P036 is exposed for a long time to direct sunlight or a fluorescent light. To protect the contents from being erased, mask the window with the opaque film. NEC attaches quality-tested opaque film to the UV EPROM products for shipping. 2. To erase the memory contents, the distance between the ultraviolet ray lamp and the PD75P036 should be 2.5 cm or less. Remark The time required for erasure changes depending on the degradation of the ultraviolet ray lamp and the surface condition (dirt) of the window. 22 PD75P036 4. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 C) Parameter Supply voltage Input voltage Output voltage Output current, high Output current, low Symbol VDD VPP VI1 VI2 VO IOH IOL Note Test Conditions Ratings -0.3 to +7.0 -0.3 to +13.5 -0.3 to VDD+0.3 -0.3 to +11 -0.3 to VDD+0.3 -10 peak value r.m.s. value peak value r.m.s. value peak value r.m.s. value Total for 0, 2, 10 Operating ambient temperature Storage temperature TA Tstg peak value r.m.s. value -30 30 15 20 5 170 120 30 20 -40 to +70 -65 to +150 Unit V V V V V mA mA mA mA mA mA mA mA mA mA C C 5 Other than ports 4, 5, or 10 Ports 4, 5 and 10 Open-drain Per pin All pins Ports 0, 3, 4 and 5 Per pin Other than ports 0, 3, 4 and 5 Per pin Total for ports 0, 3-9, 11 Note r.m.s. values should be calculated as follows: [r.m.s. value] = [peak value] x Duty Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, or even momentarily. In other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. 5 Capacitance (TA = 25 C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO Test Conditions f = 1 MHz Unmeasured pins returned to 0 V MIN. TYP. MAX. 15 15 15 Unit pF pF pF 23 PD75P036 Main System Clock Oscillator Characteristics (TA = -40 to +70 C, VDD = 2.7 to 6.0 V) Resonator Ceramic resonator Recommended Constants X1 C1 VDD Crystal resonator Oscilaltion frequency (fX) Note 1 Oscillation stabilization time Note 2 2.0 VDD = 4.5 to 6.0 V 4.19 5.0 Note 3 MHz 10 30 VDD External clock X1 input frequency (fX) Note 1 X1 input high- and low-level widths (tXH, tXL) 2.0 100 ms ms X2 C2 Parameter Oscillation frequency (fX) Note 1 Oscillation stabilization time Note 2 Test Conditions VDD = Oscillation voltage range After VDD came to MIN. of oscillation voltage range MIN. 2.0 TYP. MAX. Unit 5.0 Note 3 MHz 4 ms X1 C1 X2 C2 5.0 Note 3 MHz 250 ns X1 X2 PD74HCU04 Notes 1. The oscillation frequency and X1 input frequency are indicated only to express the characteristics of the oscillator. For instruction execution time, refer to AC Characteristics. 2. Time required for oscillation to stabilize after VDD reaches the minimum value of the oscillation voltage range or the STOP mode has been released. 3. When the oscillation frequency is 4.19 MHz < fx 5.0 MHz, do not select PCC = 0011 as the instruction execution time: otherwise, one machine cycle is set to less than 0.95 s, falling short of the rated minimum value of 0.95 s. 5 Caution When using the oscillation circuit of the main system clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: * Keep the wiring length as short as possible. * Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of lines through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillator circuit at the same potential as VDD. Do not connect the power source pattern through which a high current flows. * Do not extract signals from the oscillation circuit. 24 PD75P036 Subsystem Clock Oscillator Characteristics (TA = -40 to +70 C, VDD = 2.7 to 6.0 V) Resonator Crystal resonator Recommended Constants Parameter Oscillation frequency (fX) Note 1 Oscillation stabilization time Note 2 Test Conditions MIN. 32 VDD = 4.5 to 6.0 V TYP. MAX. Unit kHz s s 32.768 35 1.0 2 10 XT1 XT2 R C3 C4 VDD External clock X1 X2 X1 input frequency (fX) Note 1 X1 input high-, low-level widths (tXH, tXL) 32 5 100 15 kHz s Notes 1. The oscillation frequency and XT1 input frequency are indicated only to express the characteristics of the oscillator. For instruction execution time, refer to AC Characteristics. 2. Time required for oscillation to stabilize after VDD reaches the minimum value of the oscillation voltage range. Cautions When using the oscillation circuit of the main system clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: * Keep the wiring length as short as possible. * Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of lines through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillator circuit at the same potential as VDD. Do not connect the power source pattern through which a high current flows. * Do not extract signals from the oscillation circuit. The amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce the current dissipation and therefore, the subsystem clock circuit is influenced by noise more easily than the main system clock oscillation circuit. When using th subsystem clock, therefore, exercise utmost care in wiring the circuit. 5 25 PD75P036 DC Characteristics (TA = -40 to +70 C, VDD = 2.7 to 6.0 V) Parameter Input voltage, high Symbol Test Conditions VIH1 VIH2 VIH3 VIH4 Input voltage, low VIL1 VIL2 VIL3 Output voltage, high VOH Ports 2, 3, 8, 9, 11 Ports 0, 1, 6, 7, RESET Ports 4, 5, 10 Open-drain MIN. 0.7VDD 0.8VDD 0.7VDD VDD-0.5 0 0 0 VDD-1.0 VDD-0.5 VDD = 4.5 to 6.0 V, IOL = 15 mA VDD = 4.5 to 6.0 V, IOL = 1.6 mA IOL = 400 A SB0, 1 Open-drain Pull-up Resistor 1 k Input leakage current, high ILIH1 ILIH2 ILIH3 VI = 9 V VI = VDD Other than below X1, X2, XT1, XT2 Ports 4, 5, 10 (Open-drain) Input leakage current, low ILIL1 ILIL2 Input leakage current, high ILOH1 ILOH2 VO = VDD VO = 9 V Ports 4, 5, 10 (Open-drain) Input leakage current, low Internal pull-up resistor ILOL RUI VO = 0 V Ports 0, 1, 2, 3, 6, 7, 8 (except P00) VI = VDD Internal pull-down resistor RD Port 9 VI = VDD VDD =5.0 V 10 % VDD = 3.0 V 10 % 10 10 40 70 60 k k VDD = 5.0 V 10 % VDD = 3.0 V 10 % 15 30 40 -3 80 300 VI = 0 V Other than below X1, X2, XT1, XT2 -3 -20 3 20 3 20 20 0.4 0.5 0.2VDD V V V 0.4 2.0 TYP. MAX. VDD VDD 10 VDD 0.3VDD 0.2VDD 0.4 Unit V V V V V V V V V V X1, X2, XT1, XT2 Ports 2 to 5, 8 to 11 Ports 0, 1, 6, 7, RESET X1, X2, XT1, XT2 VDD = 4.5 to 6.0 V, IOH = -1 mA IOH = -100 A Output voltage, low VOL Ports 3, 4, 5 A A A A A A A A k k 26 PD75P036 Parameter Supply current Note 1 Symbol Test Conditions IDD1 4.19 MHz Crystal IDD2 oscillator Note 2 MIN. VDD = 5 V 10% VDD = 3 V 10% HALT Note 3 Note 4 TYP. 4.5 0.9 700 300 100 20 0.5 0.1 0.1 5 MAX. 14 3 2100 900 300 60 20 10 5 15 Unit mA mA VDD = 5 V 10% VDD = 3 V 10% VDD = 3 V 10% VDD = 3 V 10% A A A A A A A A C1 = C2 = 22 pF mode IDD3 IDD4 IDD5 32.768 kHz Crystal oscillator Note 5 Operating mode HALT mode XT1 = 0 V STOP mode VDD = 5 V 10% VDD = 3 V 10% TA = 25C Note 6 IDD6 32.768 kHz Crystal oscillator STOP mode VDD = 3 V 10% Notes 1. Currents for the internal pull-up resistor are not included. 2. Including when the subsystem clock is operated. 3. High-speed mode operation (when processor clock control register (PCC) is set to 0011). 4. Low-speed mode operation (when PCC is set to 0000). 5. When operated with the subsystem clock by setting the system clock control register (SCC) to SCC3 = 1 and SCC0 = 0 to stop the main system clock operation. 6. When subsystem clock is operated by executing STOP instruction during main system clock operation. 27 PD75P036 AC CHARACTERISTICS (TA = -40 to +70 C, VDD = 2.7 to 6.0 V) Parameter CPU clock cycle time Note 1 (minimum instruction execution time = 1 machine cycle) TI0 input frequency Symbol Conditions tCY Operating on main system clock Operating on subsystem clock fTI VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V INT0 INT1, 2, 4 KR0 - 7 MIN. 0.95 3.8 114 0 0 0.48 1.8 Note 2 TYP. VDD = 4.5 to 6.0 V 122 MAX. 32 32 125 1 275 Unit s s s MHz kHz s s s s s TI0 input high-, low-level widths tTIH, tTIL Interrupt input high-, low-level tINTH, widths tINTL RESET low-level width tRSL 10 10 10 s tCY vs VDD Notes 1. The CPU clock () cycle time is determined by the oscillation frequency of the connected oscillator, system clock control register (SCC), and processor clock control register (PCC). The figure on the right is cycle time tCY vs. supply voltage VDD characteristics at the Cycle Time tCY [ s] 6 5 4 3 2 32 (During Main System Clock Operation) main system clock. 2. 2tCY or 128/fx depending on the setting of the interrupt mode register (IM0). Operation Guaranteed Range 1 0.5 0 1 2 3 4 5 6 Power Supply Voltage VDD [V] 28 PD75P036 SERIAL TRANSFER OPERATION Two-Wire and Three-Wire Serial I/O Modes (SCK: internal clock output) Parameter SCK cycle time SCK high-, low-level widths SI setup time (to SCK ) SI hold time (from SCK ) SO output delay time from SCK Symbol Test Conditions tKCY1 VDD = 4.5 to 6.0 V tKL1 tKH1 tSIK1 tKSI1 tKSO1 VDD = 4.5 to 6.0 V MIN. TYP. MAX. 1600 3800 (tKCY1/2)-50 (tKCY1/2)-150 150 400 0 250 0 1000 Unit ns ns ns ns ns ns ns ns RL = 1 k, CL = 100 pF VDD = 4.5 to 6.0 V Note 5 5 Two-Wire and Three-Wire Serial I/O Modes (SCK: external clock input) Parameter SCK cycle time SCK high-, low-level widths SI setup time (to SCK ) SI hold time (from SCK ) SO output delay time from SCK Symbol Test Conditions tKCY2 VDD = 4.5 to 6.0 V tKL2 tKH2 tSIK2 tKSI2 tKSO2 VDD = 4.5 to 6.0 V MIN. 800 3200 400 1600 100 400 0 0 TYP. MAX. Unit ns ns ns ns ns ns ns ns RL = 1 k, CL = 100 pF VDD = 4.5 to 6.0 V Note 300 1000 5 5 Note RL and CL are load resistance and load capacitance of the SO output line. 29 PD75P036 SBI Mode (SCK: internal clock output (master)) Parameter SCK cycle time SCK high-/low-level widths SB0, 1 Setup time (to SCK ) SB0, 1 hold time (from SCK ) SB0, 1 output delay time from SCK SB0, 1 from SCK SCK from SB0, 1 SB0, 1 low-level width SB0, 1 high-level width Symbol Test Conditions tKCY3 VDD = 4.5 to 6.0 V tKL3 tKH3 tSIK3 tKSI3 tKSO3 tKSB tSBK tSBL tSBH VDD = 4.5 to 6.0 V MIN. TYP. MAX. 1600 3800 (tKCY3/2)-50 (tKCY3/2)-150 150 tKCY3/2 0 250 0 1000 tKCY3 tKCY3 tKCY3 tKCY3 Unit ns ns ns ns ns ns ns ns ns ns ns ns RL = 1 k, CL = 100 pF VDD = 4.5 to 6.0 V Note SBI Mode (SCK: external clock output (master)) Parameter SCK cycle time SCK high-/low-level widths SB0, 1 setup time (to SCK ) SB0, 1 hold time (from SCK ) SB0, 1 output delay time from SCK SB0, 1 from SCK SCK from SB0, 1 SB0, 1 low-level width SB0, 1 high-level width Symbol Test Conditions tKCY4 VDD = 4.5 to 6.0 V tKL4 tKH4 tSIK4 tKSI4 tKSO4 tKSB tSBK tSBL tSBH VDD = 4.5 to 6.0 V MIN. 800 3200 400 1600 100 tKCY4/2 0 0 tKCY4 tKCY4 tKCY4 tKCY4 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns RL = 1 k, CL = 100 pF VDD = 4.5 to 6.0 V Note 300 1000 Note RL and CL are load resistance and load capacitance of the SO output line. 30 PD75P036 A/D Converter (TA = -40 to +70C, VDD = 2.7 to 6.0 V, AVSS = VSS = 0 V) Parameter Resolution Absolute accuracy Symbol Test conditions Note 1 MIN. 8 TYP. 8 2.5 V AVREF+ AVDD -10 TA 70 C -40 TA -10 C tCONV tSAMP VIAN AVDD AVREF+ AVREF- RAN AIREF Conversion time Note 2 Sampling time Note 3 Analog input voltage Analog supply voltage Reference input voltage Note 4 Reference input voltage Note 4 Analog input high impedance AVREF current 2.5 V (AVREF+) - (AVREF-) 2.5 V (AVREF+) - (AVREF-) AVREF- 2.5 2.5 0 1000 0.35 MAX. 8 1.5 2.0 168/fx 44/fx AVREF+ VDD AVDD 1.0 2.0 Unit bit LSB LSB s s V V V V M mA Notes 1. Absolute accuracy from which quantization error (1/2 LSB) is removed. 2. Time until conversion end (EOC = 1) after conversion start instruction execution (40.1 s: Operation at fx = 4.19 MHz). 3. Time until sampling end after conversion start instruction execution (10.5 s: Operation at fx = 4.19 MHz). 4. (AVREF+) - (ABREF-) should be 2.5 V or more. 31 PD75P036 AC Timing Test Point (excluding X1 and XT1 inputs) 0.8 VDD 0.2 VDD Test Points 0.8 VDD 0.2 VDD Clock Timing 1/fx tXL tXH VDD - 0.5 V 0.4 V X1 Input TI0 Timing 1/fXT tXTL tXTH VDD - 0.5 V 0.4 V XT1 Input 1/fTI tTIL tTIH TI0 32 PD75P036 Serial Transfer Timing Three-Wire Serial I/O Mode: tKCY1 tKL1 tKH1 SCK tSIK1 tKSI1 SI tKSO1 Input Data SO Output Data Two-Wire Serial I/O Mode: tKCY2 tKL2 tKH2 SCK tSIK2 tKSI2 SB0,1 tKSO2 33 PD75P036 Serial Transfer Timing Bus Release Signal Transfer tKCY3,4 tKL3,4 SCK tKSB SB0,1 tSBL tSBH tSBK tSIK3,4 tKSI3,4 tKH3,4 tKSO3,4 Command Signal Transfer tKCY3,4 tKL3,4 SCK tKSB SB0,1 tSBK tSIK3,4 tKSI3,4 tKH3,4 tKSO3,4 Interrupt Input Timing tINTL INT0,1,2,4 KR0 - 7 tINTH RESET Input Timing tRSL RESET 34 PD75P036 Data Memory STOP Mode: Low-voltage Data Retention Characteristics (TA = -40 to +70 C) Parameter Data retention supply voltage Data retention supply current Note 1 Release signal set time Oscillation stabilization wait time Note 2 Symbol Test Conditions VDDDR IDDDR VDDDR = 2.0 V tSREL tWAIT Released by RESET Released by interrupt MIN. 2.0 TYP. 0.1 MAX. 6.0 10 Unit V A 0 2 /fx Note 3 17 s ms ms Notes 1. Does not include current in the internal pull-up resistor 2. The oscillation stabilization wait time is the time during which the CPU is stopped to prevent unstable operation when oscillation is started. 3. Depends on the setting of the basic interval timer mode register (BTM) as follows: BTM3 -- -- -- -- BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 0 1 1 1 WAIT time ( ): fx = 4.19 MHz 220/fx (approx. 250 ms) 217/fx (approx. 31.3 ms) 215/fx (approx. 7.82 ms) 213/fx (approx. 1.95 ms) Data Retention Timing (releasing STOP mode by RESET) Internal reset operation HALT mode STOP mode Data retention mode VDD VDDDR STOP instruction execution RESET tSREL Operating mode tWAIT Data Retention Timing (standby release signal: releasing STOP mode by interrupt) HALT mode STOP mode Data retention mode VDD VDDDR STOP instruction execution Standby release signal (interrupt request) tWAIT tSREL Operating mode 35 PD75P036 5 DC Programming Characteristics (TA = 25 5 C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V) Parameter Input voltage, high Input voltage, low Input leakage current Output voltage, high Output voltage, low VDD supply current VPP supply current Symbol VIH1 VIH2 VIL1 VIL2 ILI VOH VOL IDD IPP Test Conditions Other than X1 or X2 X1 and X2 Other than X1 or X2 X1 and X2 VIN = VIL or VIH IOH = -1 mA IOL = 1.6 mA MD0 = VIL, MD1 = VIH MIN. 0.7VDD VDD-0.5 0 0 VDD-1.0 0.4 30 30 TYP. MAX. VDD VDD 0.3VDD 0.4 10 Unit V V V V A V V mA mA Cautions 1. VPP must not exceed +13.5 V, including the overshoot. 2. Apply VDD before VPP and disconnect it after VPP. 5 AC Programming Characteristics (TA = 25 5 C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V) Parameter Symbol Note 1 Address setup time Note 2 (to MD0 ) tAS tAS MD1 setup time (to MD0 ) tM1S tOES Data setup time (to MD0 ) tDS tDS Address hold time Note 2 (from MD0 ) tAH tAH Data hold time (from MD0 ) tDH tDH Data output float delay time from MD0 tDF tDF VPP setup time (to MD3 ) tVPS tVPS VDD setup time (to MD3 ) tVDS tVCS Initialized program pulse width tPW tPW Additional program pulse width tOPW tOPW MD0 setup time (to MD1 ) tMOS tCES Data output delay time from MD0 tDV tDV MD1 hold time (from MD0 ) tM1H tOEH MD1 recovery time (from MD0 ) tM1R tOR Program counter reset time tPCR -- X1 input high-/low-level width tXH, tXL -- X1 input frequency fX -- Initial mode set time tI -- MD3 setup time (to MD1 ) tM3S -- MD3 hold time (from MD1 ) tM3H -- MD3 setup time (from MD0 ) tM3SR -- Address Note 2 to data output delay time Address Note 2 to data output hold time MD3 hold time (from MD0 ) tDAD tHAD tM3HR tACC tOH -- -- Test Conditions MIN. TYP. 2 2 2 2 2 0 2 2 0.95 1.0 0.95 2 2 2 10 0.125 4.19 2 2 2 2 2 0 2 2 130 MAX. Unit s s s s s ns s s ms ms s s s s s s MHz s s s 130 1.05 21.0 1 MD0 = MD1 = VIL tM1H + tM1R 50 s Data output float delay time from MD3 tDFR When data is read program memory When data is read program memory When data is read program memory When data is read program memory When data is read program memory from from from from from s s ns s s Notes 1. These symbols are correspond to PD27C256A symbols. 2. The internal address signal is incremented by 1 at the rising edge of fourth X1 input. The internal address is not connected to any pin. 36 PD75P036 Program Memory Write Timing 5 VPP VPP VDD VDD + 1 VDD tVPS tVDS tXH VDD X1 P40-P43 P50-P53 tI MD0 tPW MD1 tPCR MD2 tM3S MD3 tM3H tM1S tM1H tM1R tMOS tOPW Data input Data output tXL Data input tDS tDH tAH tAS Data input tDS tOH tDV tDF Program Memory Read Timing tVPS VPP VPP VDD tVDS VDD VDD + 1 VDD tXH 5 X1 P40-P43 P50-P53 tI MD0 tXL tHAD tDAD Data output tM3HR tDFR Data output tDV MD1 tPCR MD2 tM3SR MD3 37 PD75P036 5 5. CHARACTERISTIC CURVES (REFERENCE VALUES) IDD vs VDD (4.19-MHz Main System Clock, Crystal Resonator) (TA = 25 C) 5.0 PCC = 0011 PCC = 0010 3.0 PCC = 0000 Main system clock HALT mode + 32 kHz oscillation 1.0 0.5 Supply Current IDD [mA] Subsystem clock HALT mode Subsystem clock HALT mode 0.1 0.05 Main system clock STOP mode + 32 kHz oscillation 0.01 0.005 X1 XT2 X2 XT1 Crystal Crystal resonator resonator 330 k 4.19 MHz 32.768 kHz 22 pF VDD 18 pF VDD 6 8 18 pF 22 pF 0.001 0 2 4 Supply Voltage VDD [V] 38 PD75P036 IDD vs VDD (2.0-MHz Main System Clock, Crystal Resonator) (TA = 25 C) 5.0 PCC = 0011 PCC = 0010 PCC = 0000 1.0 Main system clock HALT mode + 32 kHz oscillation 0.5 3.0 Supply Current IDD [mA] Subsystem clock HALT mode 0.1 Subsystem clock HALT mode 0.05 Main system clock STOP mode + 32 kHz oscillation 0.01 0.005 X1 XT2 X2 XT1 Crystal Crystal resonator resonator 330 k 2.0 MHz 32.768 kHz 22 pF VDD 18 pF VDD 6 8 18 pF 22 pF 0.001 0 2 4 Supply Voltage VDD [V] 39 PD75P036 IDD vs VDD (4.19-MHz Main System Clock, Ceramic Resonator) (TA = 25 C) PCC = 0011 5.0 PCC = 0010 3.0 PCC = 0000 1.0 Main system clock HALT mode + 32 kHz oscillation 0.5 Supply Current IDD [mA] Subsystem clock HALT mode 0.1 Subsystem clock HALT mode 0.05 Main system clock STOP mode + 32 kHz oscillation 0.01 0.005 X1 XT2 X2 XT1 Ceramic Crystal resonator resonator 330 k 4.19 MHz 32.768 kHz 30 pF VDD 18 pF VDD 6 8 18 pF 30 pF 0.001 0 2 4 Supply Voltage VDD [V] 40 PD75P036 IDD vs VDD (20-MHz Main System Clock, Ceramic Resonator) (TA = 25 C) 5.0 PCC = 0011 PCC = 0010 PCC = 0000 1.0 3.0 Main system clock HALT mode + 32 kHz oscillation 0.5 Supply Current IDD [mA] Subsystem clock HALT mode 0.1 Subsystem clock HALT mode 0.05 Main system clock STOP mode + 32 kHz oscillation 0.01 0.005 X1 XT2 X2 XT1 Ceramic Crystal resonator resonator 330 k 2.0 MHz 32.768 kHz 30 pF VDD 18 pF VDD 6 8 18 pF 30 pF 0.001 0 2 4 Supply Voltage VDD [V] 41 PD75P036 IDD vs fx 5 X1 X2 IDD vs fx 2.0 X1 X2 (VDD = 5 V, TA = 25 C) (VDD = 3 V, TA = 25 C) PCC = 0011 4 1.5 PCC = 0010 3 IDD [mA] IDD [mA] 1.0 PCC = 0010 PCC = 0000 2 PCC = 0000 0.5 1 Main system clock HALT mode Main system clock HALT mode 0 0 1 2 3 fx [MHz] 4 5 6 0 0 1 2 3 fx [MHz] 4 5 6 IOL vs VOL (Port 0) 40 (TA = 25C) 30 IOL vs VOL (Ports 2, 6 to 10) (TA = 25C) 25 30 VDD = 6 V VDD = 5 V VDD = 4 V IOL [mA] 20 VDD = 6 V VDD = 5 V VDD = 4 V 20 IOL [mA] 15 VDD = 3 V VDD = 3 V 10 VDD = 2.7 V 10 VDD = 2.7 V 5 0 0 1 2 3 VOL [V] 4 5 0 0 1 2 3 VOL [V] 4 5 42 PD75P036 IOL vs VOL (Ports 3 to 5) 40 (TA = 25C) 30 VDD = 6 V VDD = 5 V VDD = 4 V IOL [mA] 20 VDD = 3 V VDD = 2.7 V 10 0 0 1 2 3 VOL [V] 4 5 IOH vs VDD-VOH 15 (TA = 25C) 10 VDD = 6 V VDD = 5 V VDD = 4 V IOH [mA] VDD = 3 V VDD = 2.7 V 5 0 0 1 2 3 VDD - VOH [V] 4 5 43 PD75P036 6. PACKAGE DRAWINGS 64 PIN PLASTIC SHRINK DIP (750 mil) 64 33 1 A 32 K L J I F D G H N M C B M R NOTE 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel. ITEM MILLIMETERS A B C D F G H I J K L M N R 58.68 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 19.05 (T.P.) 17.0 0.25 +0.10 -0.05 0.17 0~15 INCHES 2.311 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.750 (T.P.) 0.669 0.010 +0.004 -0.003 0.007 0~15 P64C-70-750A,C-1 44 PD75P036 64 PIN PLASTIC QFP ( 14) A B 48 49 33 32 detail of lead end C D S 64 1 17 16 F G H IM J K P N L P64GC-80-AB8-3 ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 17.6 0.4 14.0 0.2 14.0 0.2 17.6 0.4 1.0 1.0 0.35 0.10 0.15 0.8 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.10 2.55 0.1 0.1 2.85 MAX. INCHES 0.693 0.016 0.551+0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.039 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 0.008 0.031+0.009 -0.008 0.006+0.004 -0.003 0.004 0.100 0.004 0.004 0.112 MAX. NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. M 55 Q 45 PD75P036 5 64 PIN CERAMIC WQFN A B R S H J I M Q T U CD 64 U1 K E G F Z NOTE Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A B C D E F G H I J K Q R S T U U1 W Z 13.80.25 13.0 12.4 13.80.25 1.94 2.14 3.56 MAX. 0.510.1 0.08 0.8 (T.P.) 1.00.15 C 0.3 0.9 0.9 R 1.5 6.0 1.0 0.750.15 0.10 INCHES 0.543+0.011 -0.010 0.512 0.488 0.543 +0.011 -0.010 0.076 0.084 0.141 MAX. 0.0200.004 0.003 0.031 (T.P.) 0.0390.006 C 0.012 0.035 0.035 R 0.059 0.236 0.039 0.030 +0.006 -0.007 0.004 X64KG-80A-1 W 1 46 PD75P036 7. RECOMMENDED SOLDERING CONDITIONS It is recommended that the PD75P036 be soldered under the following conditions. For details on the recommended soldering conditions, refer to Information Document "Semiconductor Devices Mounting Technology Manual" (IEI-1207). For soldering methods and conditions other than those recommended, please contact your NEC sales representative. Table 7-1. Soldering Conditions for Surface Mount Devices PD75P036GC-AB8: 64-pin plastic QFP (14 x 14 mm) Soldering Method Wave soldering Soldering Conditions Soldering bath temperature: 260C max., Time: 10 seconds max., Number of times: 1, Maximum number of days: 2 daysNote, (thereafter, 16 hours of prebaking is required at 125C), Preheating temperature: 120C max. (package surface temperature). Package peak temperature: 230C, Time: 30 seconds max. (210C min.), Number of times: 1, Maximum number of days: 2 daysNote (thereafter, 16 hours of prebaking is required at 125C) VPS Package peak temperature: 215C, Time: 40 seconds max. (200C min.), Number of times: 1, Maximum number of days: 2 daysNote (thereafter, 16 hours of prebaking is required at 125C) Pin temperature: 300C max., Time: 3 seconds max. (per pin row) VP15-162-1 Recommended Soldering Code WS60-162-1 Infrared reflow IR30-162-1 Partial heating -- Note Number of days after unpacking the dry pack. Storage conditions are 25C and 65% RH max. Caution Do not use different soldering methods together (except the partial heating method). Table 7-2. Soldering Conditions for Through-hole Devices PD75P036CW: 64-pin Plastic Shrink DIP (750 mils) Soldering Method Wave soldering (pin only) Partial heating Soldering Conditions Soldering bath temperature: 260C max., Time: 10 seconds max. Pin temperature: 300C max., Time: 3 seconds max. (per pin row) Caution Apply wave soldering only to the lead part and be careful so as not to bring solder into direct contact with the device body. 47 PD75P036 5 APPENDIX A. DEVELOPMENT TOOLS The following development tools are readily available to support development of systems using PD75P03s: Hardware IE-75000-R Note 1 IE-75001-R IE-75000-R-EM Note 2 EP-75028CW-R EP-75028GC-R EV-9200GC-64 PG-1500 PA-75P036CW PA-75P036GC In-circuit emulator for 75K series Emulation board for IE-75000-R and IE-75001-R Emulation prove for PD75P036CW Emulation prove for PD75P036GC. Provided with 64-pin conversion socket. EV-9200G-80 used for PD75P036GC/75P036KG PROM programmer PROM programmer adapter used for PD75P036CW. It is connected to PG-1500. PROM programmer adapter used for PD75P036GC. It is connected to PG-1500. Host machine * PC-9800 series (MS-DOSTM Ver. 3.30 to Ver. 5.00A Note 3) * IBM PC/ATTM (Refer to document OS for IBM PC) Software IE control program PG-1500 controller RA75X relocatable assembler Notes 1. For maintenance purpose only 2. Not provided with IE-75001-R 3. Ver.5.00/5.00A has a task swap function, but this function cannot be used with these software. Remark Please refer to the 75X SERIES SELECTION GUIDE (IF-1027) for information on third party development tools. OS for IBM PC The following OS are supported for IBM PC. OS PC DOSTM MS-DOS IBM DOSTM Version Ver. 3.1 to Ver. 6.3 J6.1/VNote to 16.3/VNote Ver. 5.0 to Ver. 6.2 5.0/VNote to J6.2/VNote J5.02/VNote Note Supported only English mode. Caution Ver. 5.0 or later has a task swap function, but this function cannot be used with these software. 48 PD75P036 APPENDIX B. RELATED DOCUMENTS Please use this document in conjunction with the following. Related document may be "Preliminary." However, in this document, "Preliminary" is not indicated. 5 Device Document Title PD75P036 Data Sheet (This document) PD75028 User's Manual PD75028 Instruction List PD75028 Application Note -- Basics 75X series Selection Guide Document Number Japanese English IC-7914 IC-2967 IEU-694 IEU-1280 IEM-5511 -- IEA-689 IEA-1277 IF-151 IF-1027 Development Tool Document Title Hardware IE-75000-R/IE-75001-R User's Manual IE-75000-R-EM User's Manual EP-75028CW-R User's Manual IE-75028GC-R User's Manual PG-1500 User'ss Manual RA75X Assembler Package User's Manual PG-1500 Controller User's Manual Document Number Japanese EEU-846 EEU-673 EEU-697 EEU-692 EEU-651 EEU-731 EEU-730 EEU-704 EEU-5008 English EEU-1416 EEU-1294 EEU-1314 EEU-1306 EEU-1335 EEU-1346 EEU-1363 Scheduled EEU-1291 Software Operation Language PC-9800 series (MS-DOS) based IBM PC series (PC DOS) based 49 PD75P036 Other Document Title Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Devices Microcomputer-Related Product Guide -- Third Party Products Number Japanese IEI-635 IEI-616 IEI-620 IEM-5068 MEM-539 MEI-603 MEI-604 English IEI-1213 IEI-1207 IEI-1209 -- -- MEI-1202 -- Caution The contents of the documents listed above are subject to change without prior notice to user's. Make sure to use the latest edition when starting design. 50 PD75P036 NOTES FOR CMOS DEVICES (1) PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. (2) HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input lelvel may be generated due to noise, etc., hence causing mulfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. (3) STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 51 PD75P036 MS-DOS is a trademark of Microsoft Corporation. IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation. The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may prohibited without governmental license. To export or re-export some or all or these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. License not needed: PD75P036KG The customer must judge the need for license: PD75P036CW, 75P036GC-AB8 No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties b y or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standatd", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computer, office equipment, communication equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical eqiupment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nucleare reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M4 94.11 |
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